Programmable logic devices such as field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) are configured by a user to perform a desired logical function. This configuration involves a programming or configuration of a configuration memory in the devices. For example, in a field programmable logic device (FPGA), the configuration memory programs the truth table for look-up tables and programmable interconnects. In this fashion, the programmed FPGA can implement a desired logical function during operation.
In general, substantial portions of an FPGA's logical resources remain unused during user operation. If not used for other purposes, the configuration memory corresponding to the unused logical resources remains fallow as well. Thus, it is conventional for an FPGA to supplement its embedded RAM by configuring unused portions of the configuration memory as distributed random access memory (RAM) during user operation of the device. Since the unused memory is not storing any truth tables or other necessary configuration data, there is no harm in writing over the unused portions designated as RAM during user operation.
The use of configuration memory as RAM makes the resulting FPGA less costly to manufacture in that the need for additional die space for RAM is alleviated. However, an issue arises during use in that configuration memory, like other types of memory, can suffer from soft errors. Even though a memory may be constructed correctly, events such as cosmic rays or other types of radiation can readily change the bit stored by one of its memory cells. In an FPGA, such a soft error is actually a “firm” error in that the entire programming of the device may be ruined by just a single bit error in the necessary configuration data. Thus, it is conventional for configuration memories to be repeatedly analyzed for any soft error events during device operation. Such soft error detection (SED) is typically performed by first calculating a cyclic redundancy check (CRC) checksum for the configuration data prior to configuring the device. After configuration and during operation, the CRC is repeatedly calculated by retrieving the configuration data from the configuration memory and running the CRC algorithm on the retrieved data accordingly. The presence of any errors in the configuration data is thus revealed by a corresponding change in the CRC checksum. Upon detection of corrupt configuration data, the hardware or software in the FPGA controlling the SED function can then command the FPGA to reconfigure the configuration memory.
Configuration memory being used as RAM during normal operation of the FPGA will naturally have its content change as data is written or re-written to the RAM portions. The RAM configuration memory portions must thus be blocked from readback while the SED function is implemented or the normal RAM content change could be interpreted as corruption of the configuration data. For example, it is conventional to block readback of the RAM portions through a modification of the data shift register (DSR) used to shift in the configuration data to the device. But such modification can result in the DSR having less sensitive sense amplifiers. Alternatively, the readback blocking can be performed using a combination of control logic, latches, and counters. But such an alternative adds to design complexity and increases costs. Accordingly, there is a need in the art for improved readback blocking for programmable logic devices.